# hinv -v
CPU Board at Slot 2: (Enabled)
  Processor 0 at Slot 2/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 1 at Slot 2/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 2 at Slot 2/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 3 at Slot 2/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
CPU Board at Slot 3: (Enabled)
  Processor 4 at Slot 3/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 5 at Slot 3/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 6 at Slot 3/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 7 at Slot 3/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
CPU Board at Slot 4: (Enabled)
  Processor 8 at Slot 4/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 9 at Slot 4/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 10 at Slot 4/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 11 at Slot 4/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
Secondary unified instruction/data cache size: 2 Mbytes
Data cache size: 32 Kbytes
Instruction cache size: 32 Kbytes
Main memory size: 2048 Mbytes, 2-way interleaved
MC3 Memory Board at Slot 1: 2048 MB of memory (Enabled)
  Bank A contains 64 MB SIMMS (Enabled)
  Bank B contains 64 MB SIMMS (Enabled)
  Bank C contains 64 MB SIMMS (Enabled)
  Bank D contains 64 MB SIMMS (Enabled)
  Bank E contains 64 MB SIMMS (Enabled)
  Bank F contains 64 MB SIMMS (Enabled)
  Bank G contains 64 MB SIMMS (Enabled)
  Bank H contains 64 MB SIMMS (Enabled)
I/O board, Ebus slot 5: IO4 revision 1
Integral EPC serial ports: 4
Integral Ethernet controller: et0, Ebus slot 5
FDDIXPress controller: ipg0, version 1
EPC external interrupts
Integral SCSI controller 4: Version WD33C95A, differential, revision 1
Integral SCSI controller 3: Version WD33C95A, differential, revision 1
Integral SCSI controller 2: Version WD33C95A, differential, revision 1
Integral SCSI controller 1: Version WD33C95A, single ended, revision 0
  Disk drive: unit 1 on SCSI controller 1
Integral SCSI controller 0: Version WD33C95A, single ended, revision 0