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   "key": "ret",
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   "attrs": {}
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  {
   "family": "storage",
   "key": "cdrom",
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   "attrs": {}
  },
  {
   "family": "graphics",
   "key": "kona",
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     "lines": [
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   "gaps": [],
   "text": "CPU Board at Slot 5: (Enabled)\n  Processor 0 at Slot 5/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)\n  Processor 1 at Slot 5/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)\n  Processor 2 at Slot 5/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)\n  Processor 3 at Slot 5/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)\nCPU Board at Slot 8: (Enabled)\n  Processor 4 at Slot 8/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)\n  Processor 5 at Slot 8/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)\n  Processor 6 at Slot 8/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)\n  Processor 7 at Slot 8/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)\nCPU: MIPS R10000 Processor Chip Revision: 2.5\nFPU: MIPS R10010 Floating Point Chip Revision: 0.0\nMain memory size: 1536 Mbytes, 4-way interleaved\nMC3 Memory Board at Slot 1: 768 MB of memory (Enabled)\n  Bank A contains 64 MB SIMMS (Enabled)\n  Bank B contains 64 MB SIMMS (Enabled)\n  Bank C contains 16 MB SIMMS (Enabled)\n  Bank D contains 16 MB SIMMS (Enabled)\n  Bank E contains 16 MB SIMMS (Enabled)\n  Bank F contains 16 MB SIMMS (Enabled)\nMC3 Memory Board at Slot 4: 768 MB of memory (Enabled)\n  Bank A contains 64 MB SIMMS (Enabled)\n  Bank B contains 64 MB SIMMS (Enabled)\n  Bank C contains 16 MB SIMMS (Enabled)\n  Bank D contains 16 MB SIMMS (Enabled)\n  Bank E contains 16 MB SIMMS (Enabled)\n  Bank F contains 16 MB SIMMS (Enabled)\nInstruction cache size: 32 Kbytes\nData cache size: 32 Kbytes\nSecondary unified instruction/data cache size: 2 Mbytes\nIntegral SCSI controller 0: Version WD33C95A, single ended, revision 0\nIntegral SCSI controller 1: Version WD33C95A, differential, revision 0\n  Disk drive: unit 1 on SCSI controller 1 (unit 1)\nIntegral SCSI controller 90: Version WD33C95A, single ended, revision 0\nIntegral SCSI controller 91: Version WD33C95A, differential, revision 0\nIntegral SCSI controller 92: Version SCIP/WD33C95A, differential\nIntegral SCSI controller 93: Version SCIP/WD33C95A, differential\nIntegral SCSI controller 94: Version SCIP/WD33C95A, differential\n  Disk drive: unit 1 on SCSI controller 94 (unit 1)\n  Disk drive: unit 2 on SCSI controller 94 (unit 2)\n  Disk drive: unit 3 on SCSI controller 94 (unit 3)\n  Disk drive: unit 4 on SCSI controller 94 (unit 4)\nASO 6-port Serial board 0: revision 3.1.26, Ebus slot 11, IO Adapter 6\n"
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  {
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   "credit": null,
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   "archive_url": null,
   "tags": [],
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   "gaps": [],
   "text": "Graphics board 0 is \"KONAS\" graphics.\n        Managed (\":0.0\") 1280x1024\n        Display has 2 channels\n        4 GEs (of 4), occmask = 0x0f\n        4MB external BEF ram, 32bit path\n        1 RM6 board (of 1) 1/0/0/0\n        Texture Memory: 64MB/-/-/-\n        Medium pixel depth\n        32K cmap\n"
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  {
   "kind": "irix-hinv",
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   "os_release": null,
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   "text": "CPU Board at Slot 4: (Enabled)\n  Processor 0 at Slot 4/Slice 0: 200 Mhz R4400 with 4 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 6.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 1 at Slot 4/Slice 1: 200 Mhz R4400 with 4 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 6.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 2 at Slot 4/Slice 2: 200 Mhz R4400 with 4 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 6.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 3 at Slot 4/Slice 3: 200 Mhz R4400 with 4 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 6.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\nCPU Board at Slot 5: (Enabled)\n  Processor 4 at Slot 5/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 5 at Slot 5/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 6 at Slot 5/Slice 2: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 7 at Slot 5/Slice 3: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\nCPU Board at Slot 6: (Enabled)\n  Processor 8 at Slot 6/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 9 at Slot 6/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 10 at Slot 6/Slice 2: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 11 at Slot 6/Slice 3: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\nCPU Board at Slot 8: (Enabled)\n  Processor 12 at Slot 8/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 13 at Slot 8/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 14 at Slot 8/Slice 2: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 15 at Slot 8/Slice 3: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\nCPU Board at Slot 10: (Enabled)\n  Processor 16 at Slot 10/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 17 at Slot 10/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 18 at Slot 10/Slice 2: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\n  Processor 19 at Slot 10/Slice 3: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 5.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\nMain memory size: 1024 Mbytes, 2-way interleaved\nMC3 Memory Board at Slot 1: 256 MB of memory (Enabled)\n  Bank A contains 16 MB SIMMS (Enabled)\n  Bank B contains 16 MB SIMMS (Enabled)\n  Bank C contains 16 MB SIMMS (Enabled)\n  Bank D contains 16 MB SIMMS (Enabled)\nMC3 Memory Board at Slot 2: 512 MB of memory (Enabled)\n  Bank A contains 16 MB SIMMS (Enabled)\n  Bank B contains 16 MB SIMMS (Enabled)\n  Bank C contains 16 MB SIMMS (Enabled)\n  Bank D contains 16 MB SIMMS (Enabled)\n  Bank E contains 16 MB SIMMS (Enabled)\n  Bank F contains 16 MB SIMMS (Enabled)\n  Bank G contains 16 MB SIMMS (Enabled)\n  Bank H contains 16 MB SIMMS (Enabled)\nMC3 Memory Board at Slot 3: 256 MB of memory (Enabled)\n  Bank A contains 16 MB SIMMS (Enabled)\n  Bank B contains 16 MB SIMMS (Enabled)\n  Bank C contains 16 MB SIMMS (Enabled)\n  Bank D contains 16 MB SIMMS (Enabled)\nInstruction cache size: 16 Kbytes\nData cache size: 16 Kbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nIntegral SCSI controller 0: Version WD33C95A, differential, revision 0\nIntegral SCSI controller 1: Version WD33C95A, differential, revision 0\n  Disk drive: unit 1 on SCSI controller 1 (unit 1)\nIntegral SCSI controller 2: Version SCIP/WD33C95A, single ended\nIntegral SCSI controller 3: Version SCIP/WD33C95A, differential\nIntegral SCSI controller 4: Version SCIP/WD33C95A, differential\nIntegral SCSI controller 5: Version SCIP/WD33C95A, differential\nIntegral SCSI controller 6: Version SCIP/WD33C95A, differential\n  Disk drive: unit 1 on SCSI controller 6 (unit 1)\n  Disk drive: unit 2 on SCSI controller 6 (unit 2)\nIntegral SCSI controller 7: Version SCIP/WD33C95A, differential\n  Disk drive: unit 1 on SCSI controller 7 (unit 1)\n  Disk drive: unit 2 on SCSI controller 7 (unit 2)\n  Disk drive: unit 3 on SCSI controller 7 (unit 3)\n"
  },
  {
   "kind": "irix-gfxinfo",
   "command": "gfxinfo -v",
   "os_release": null,
   "source_date": "1997-04",
   "credit": null,
   "source_url": "http://www.sgidepot.co.uk/simonpigot/OnyxRealityEngine2.html",
   "archive_url": null,
   "tags": [],
   "items": [
    {
     "family": "graphics",
     "key": "rev",
     "label": "REV",
     "count": 1,
     "lines": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8
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    }
   ],
   "gaps": [],
   "text": "Graphics board 0 is \"REV\" graphics.\n        Managed (\":0.0\") 1280x1024\n        Display 1280x1024 @ 72Hz\n        12 GE (GE10 rev. 0x7)\n        2 RM5 boards\n        Medium pixel depth\n        10-bit RGBA pixels\n        Not using Multi-Channel Option\n"
  },
  {
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   "credit": null,
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   "archive_url": null,
   "tags": [],
   "items": [
    {
     "family": "board",
     "key": "cpu-board",
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     "count": 1,
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    {
     "family": "cpu",
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     "attrs": {
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     "lines": [
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     "family": "cpu",
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    {
     "family": "memory",
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     "attrs": {
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     "lines": [
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    },
    {
     "family": "board",
     "key": "mc3-memory-board",
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     "count": 1,
     "attrs": {
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     "lines": [
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    },
    {
     "family": "scsi",
     "key": "wd33c95a",
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    {
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     "label": "Disk",
     "count": 3,
     "lines": [
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    }
   ],
   "gaps": [],
   "text": "CPU Board at Slot 2: (Enabled)\n  Processor 0 at Slot 2/Slice 0: 90 Mhz R8000 with 4 MB secondary cache (Enabled)\n  Processor 1 at Slot 2/Slice 1: 90 Mhz R8000 with 4 MB secondary cache (Enabled)\nCPU: MIPS R8000 Processor Chip Revision: 3.0\nFPU: MIPS R8010 Floating Point Chip Revision: 0.2\nMain memory size: 512 Mbytes, 2-way interleaved\nMC3 Memory Board at Slot 1: 512 MB of memory (Enabled)\n  Bank A contains 16 MB SIMMS (Enabled)\n  Bank B contains 16 MB SIMMS (Enabled)\n  Bank C contains 16 MB SIMMS (Enabled)\n  Bank D contains 16 MB SIMMS (Enabled)\n  Bank E contains 16 MB SIMMS (Enabled)\n  Bank F contains 16 MB SIMMS (Enabled)\n  Bank G contains 16 MB SIMMS (Enabled)\n  Bank H contains 16 MB SIMMS (Enabled)\nInstruction cache size: 16 Kbytes\nData cache size: 16 Kbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nIntegral SCSI controller 0: Version WD33C95A, single ended, revision 0\n  Disk drive: unit 1 on SCSI controller 0 (unit 1)\nIntegral SCSI controller 1: Version WD33C95A, differential, revision 0\n  Disk drive: unit 1 on SCSI controller 1 (unit 1)\n  Disk drive: unit 3 on SCSI controller 1 (unit 3)\n"
  },
  {
   "kind": "irix-gfxinfo",
   "command": "gfxinfo -v",
   "os_release": null,
   "source_date": "1997-04",
   "credit": null,
   "source_url": "http://www.sgidepot.co.uk/simonpigot/OnyxRealityEngine2.html",
   "archive_url": null,
   "tags": [],
   "items": [
    {
     "family": "graphics",
     "key": "ret",
     "label": "RET",
     "count": 1,
     "lines": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9
     ]
    }
   ],
   "gaps": [],
   "text": "Graphics board 0 is \"RET\" graphics.\n        Managed (\":0.0\") 1280x2048\n        MCO Display 0 1280x1024 @ 60Hz, origin (0, 0)\n        MCO Display 1 1280x1024 @ 60Hz, origin (0, 1024)\n        12 GE (GE10 rev. 0x7)\n        2 RM5 boards\n        Small pixel depth\n        10-bit RGB pixels\n        Driving Multi-Channel Option\n"
  },
  {
   "kind": "irix-hinv",
   "command": "hinv -c",
   "os_release": null,
   "source_date": "1997-04",
   "credit": null,
   "source_url": "http://www.sgidepot.co.uk/simonpigot/OnyxRealityEngine2.html",
   "archive_url": null,
   "tags": [],
   "items": [
    {
     "family": "board",
     "key": "cpu-board",
     "label": "CPU board",
     "count": 1,
     "lines": [
      1
     ]
    },
    {
     "family": "cpu",
     "key": "r4400",
     "label": "R4400",
     "count": 4,
     "attrs": {
      "mhz": 250,
      "scache_mb": 4
     },
     "lines": [
      2,
      3,
      4,
      5
     ]
    },
    {
     "family": "cpu",
     "key": "r4400",
     "label": "R4400",
     "count": 1,
     "attrs": {
      "rev": "6.0",
      "fpu": "R4000"
     },
     "lines": [
      6,
      7
     ]
    },
    {
     "family": "memory",
     "key": "main",
     "label": "Main memory",
     "count": 1,
     "attrs": {
      "mb": 1024
     },
     "lines": [
      8
     ]
    },
    {
     "family": "board",
     "key": "mc3-memory-board",
     "label": "MC3 memory board",
     "count": 1,
     "attrs": {
      "mb": 1024
     },
     "lines": [
      9
     ]
    },
    {
     "family": "scsi",
     "key": "wd33c95a",
     "label": "WD33C95A",
     "count": 2,
     "lines": [
      17,
      19
     ]
    },
    {
     "family": "storage",
     "key": "cdrom",
     "label": "CD-ROM",
     "count": 1,
     "lines": [
      18
     ]
    },
    {
     "family": "storage",
     "key": "disk",
     "label": "Disk",
     "count": 4,
     "lines": [
      20,
      21,
      22,
      23
     ]
    },
    {
     "family": "scsi",
     "key": "scip-wd33c95a",
     "label": "SCIP/WD33C95A",
     "count": 3,
     "lines": [
      24,
      25,
      26
     ]
    }
   ],
   "gaps": [],
   "text": "CPU Board at Slot 2: (Enabled)\n  Processor 0 at Slot 2/Slice 0: 250 Mhz R4400 with 4 MB secondary cache (Enabled)\n  Processor 1 at Slot 2/Slice 1: 250 Mhz R4400 with 4 MB secondary cache (Enabled)\n  Processor 2 at Slot 2/Slice 2: 250 Mhz R4400 with 4 MB secondary cache (Enabled)\n  Processor 3 at Slot 2/Slice 3: 250 Mhz R4400 with 4 MB secondary cache (Enabled)\nCPU: MIPS R4400 Processor Chip Revision: 6.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\nMain memory size: 1024 Mbytes, 2-way interleaved\nMC3 Memory Board at Slot 1: 1024 MB of memory (Enabled)\n  Bank A contains 64 MB SIMMS (Enabled)\n  Bank B contains 64 MB SIMMS (Enabled)\n  Bank C contains 64 MB SIMMS (Enabled)\n  Bank D contains 64 MB SIMMS (Enabled)\nInstruction cache size: 16 Kbytes\nData cache size: 16 Kbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nIntegral SCSI controller 0: Version WD33C95A, single ended, revision 0\n  CDROM: unit 6 on SCSI controller 0\nIntegral SCSI controller 1: Version WD33C95A, differential, revision 0\n  Disk drive: unit 1 on SCSI controller 1 (unit 1)\n  Disk drive: unit 2 on SCSI controller 1 (unit 2)\n  Disk drive: unit 3 on SCSI controller 1 (unit 3)\n  Disk drive: unit 4 on SCSI controller 1 (unit 4)\nIntegral SCSI controller 5: Version SCIP/WD33C95A, differential\nIntegral SCSI controller 6: Version SCIP/WD33C95A, differential\nIntegral SCSI controller 7: Version SCIP/WD33C95A, differential\n"
  },
  {
   "kind": "irix-gfxinfo",
   "command": null,
   "os_release": null,
   "source_date": "1997-04",
   "credit": null,
   "source_url": "http://www.sgidepot.co.uk/simonpigot/OnyxRealityEngine2.html",
   "archive_url": null,
   "tags": [],
   "items": [
    {
     "family": "graphics",
     "key": "kona",
     "label": "KONA",
     "count": 1,
     "lines": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12
     ]
    }
   ],
   "gaps": [],
   "text": "Graphics board 0 is \"KONA\" graphics.\n        Managed (\":0.0\") 1280x1024\n        Display has 2 channels\n        4 GEs (of 4), occmask = 0x0f\n        4MB external BEF ram, 32bit path\n        1 RM6 board (of 1) 1/0/0/0\n        Texture Memory: 16MB/-/-/-\n        Medium pixel depth\n        32K cmap\n        Channel 0:\n         Origin = (0,0)\n         Video Output: 1280 pixels, 1024 lines, 72.00Hz (1280x1024_72.vfo)\n"
  },
  {
   "kind": "irix-hinv",
   "command": "hinv -c",
   "os_release": null,
   "source_date": "1997-04",
   "credit": null,
   "source_url": "http://www.sgidepot.co.uk/simonpigot/OnyxRealityEngine2.html",
   "archive_url": null,
   "tags": [],
   "items": [
    {
     "family": "cpu",
     "key": "r4400",
     "label": "R4400",
     "count": 1,
     "attrs": {
      "rev": "6.0",
      "fpu": "R4000"
     },
     "lines": [
      1,
      2
     ]
    },
    {
     "family": "board",
     "key": "cpu-board",
     "label": "CPU board",
     "count": 2,
     "lines": [
      3,
      8
     ]
    },
    {
     "family": "cpu",
     "key": "r4400",
     "label": "R4400",
     "count": 4,
     "attrs": {
      "mhz": 250,
      "scache_mb": 4
     },
     "lines": [
      4,
      5,
      6,
      7
     ]
    },
    {
     "family": "cpu",
     "key": "r4400",
     "label": "R4400",
     "count": 2,
     "attrs": {
      "mhz": 150,
      "scache_mb": 1
     },
     "lines": [
      9,
      10
     ]
    },
    {
     "family": "memory",
     "key": "main",
     "label": "Main memory",
     "count": 1,
     "attrs": {
      "mb": 256
     },
     "lines": [
      11
     ]
    },
    {
     "family": "board",
     "key": "mc3-memory-board",
     "label": "MC3 memory board",
     "count": 1,
     "attrs": {
      "mb": 256
     },
     "lines": [
      12
     ]
    },
    {
     "family": "scsi",
     "key": "wd33c95a",
     "label": "WD33C95A",
     "count": 4,
     "lines": [
      25,
      28,
      31,
      32
     ]
    },
    {
     "family": "storage",
     "key": "cdrom",
     "label": "CD-ROM",
     "count": 2,
     "lines": [
      26,
      27
     ]
    },
    {
     "family": "storage",
     "key": "disk",
     "label": "Disk",
     "count": 2,
     "lines": [
      29,
      30
     ]
    }
   ],
   "gaps": [],
   "text": "CPU: MIPS R4400 Processor Chip Revision: 6.0\nFPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0\nCPU Board at Slot 2: (Enabled)\n  Processor 0 at Slot 2/Slice 0: 250 Mhz R4400 with 4 MB secondary cache (Enabled)\n  Processor 1 at Slot 2/Slice 1: 250 Mhz R4400 with 4 MB secondary cache (Enabled)\n  Processor 2 at Slot 2/Slice 2: 250 Mhz R4400 with 4 MB secondary cache (Enabled)\n  Processor 3 at Slot 2/Slice 3: 250 Mhz R4400 with 4 MB secondary cache (Enabled)\nCPU Board at Slot 3: (Enabled)\n  Processor 4 at Slot 3/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\n  Processor 5 at Slot 3/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled)\nMain memory size: 256 Mbytes, 2-way interleaved\nMC3 Memory Board at Slot 1: 256 MB of memory (Enabled)\n  Bank A contains 16 MB SIMMS (Enabled)\n  Bank B contains 16 MB SIMMS (Enabled)\n  Bank C contains 16 MB SIMMS (Enabled)\n  Bank D contains 16 MB SIMMS (Enabled)\nInstruction cache size: 16 Kbytes\nData cache size: 16 Kbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nSecondary unified instruction/data cache size: 4 Mbytes\nSecondary unified instruction/data cache size: 1 Mbyte\nSecondary unified instruction/data cache size: 1 Mbyte\nIntegral SCSI controller 0: Version WD33C95A, single ended, revision 0\n  CDROM: unit 5 on SCSI controller 0\n  CDROM: unit 6 on SCSI controller 0\nIntegral SCSI controller 1: Version WD33C95A, differential, revision 0\n  Disk drive: unit 1 on SCSI controller 1 (unit 1)\n  Disk drive: unit 2 on SCSI controller 1 (unit 2)\nIntegral SCSI controller 40: Version WD33C95A, single ended, revision 0\nIntegral SCSI controller 41: Version WD33C95A, differential, revision 0\n"
  }
 ]
}
