# hinv -c CPU Board at Slot 5: (Enabled) Processor 0 at Slot 5/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled) Processor 1 at Slot 5/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled) Processor 2 at Slot 5/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled) Processor 3 at Slot 5/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled) CPU Board at Slot 8: (Enabled) Processor 4 at Slot 8/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled) Processor 5 at Slot 8/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled) Processor 6 at Slot 8/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled) Processor 7 at Slot 8/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled) CPU: MIPS R10000 Processor Chip Revision: 2.5 FPU: MIPS R10010 Floating Point Chip Revision: 0.0 Main memory size: 1536 Mbytes, 4-way interleaved MC3 Memory Board at Slot 1: 768 MB of memory (Enabled) Bank A contains 64 MB SIMMS (Enabled) Bank B contains 64 MB SIMMS (Enabled) Bank C contains 16 MB SIMMS (Enabled) Bank D contains 16 MB SIMMS (Enabled) Bank E contains 16 MB SIMMS (Enabled) Bank F contains 16 MB SIMMS (Enabled) MC3 Memory Board at Slot 4: 768 MB of memory (Enabled) Bank A contains 64 MB SIMMS (Enabled) Bank B contains 64 MB SIMMS (Enabled) Bank C contains 16 MB SIMMS (Enabled) Bank D contains 16 MB SIMMS (Enabled) Bank E contains 16 MB SIMMS (Enabled) Bank F contains 16 MB SIMMS (Enabled) Instruction cache size: 32 Kbytes Data cache size: 32 Kbytes Secondary unified instruction/data cache size: 2 Mbytes Integral SCSI controller 0: Version WD33C95A, single ended, revision 0 Integral SCSI controller 1: Version WD33C95A, differential, revision 0 Disk drive: unit 1 on SCSI controller 1 (unit 1) Integral SCSI controller 90: Version WD33C95A, single ended, revision 0 Integral SCSI controller 91: Version WD33C95A, differential, revision 0 Integral SCSI controller 92: Version SCIP/WD33C95A, differential Integral SCSI controller 93: Version SCIP/WD33C95A, differential Integral SCSI controller 94: Version SCIP/WD33C95A, differential Disk drive: unit 1 on SCSI controller 94 (unit 1) Disk drive: unit 2 on SCSI controller 94 (unit 2) Disk drive: unit 3 on SCSI controller 94 (unit 3) Disk drive: unit 4 on SCSI controller 94 (unit 4) ASO 6-port Serial board 0: revision 3.1.26, Ebus slot 11, IO Adapter 6 # gfxinfo -v Graphics board 0 is "KONAS" graphics. Managed (":0.0") 1280x1024 Display has 2 channels 4 GEs (of 4), occmask = 0x0f 4MB external BEF ram, 32bit path 1 RM6 board (of 1) 1/0/0/0 Texture Memory: 64MB/-/-/- Medium pixel depth 32K cmap # hinv -c CPU Board at Slot 4: (Enabled) Processor 0 at Slot 4/Slice 0: 200 Mhz R4400 with 4 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 6.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 1 at Slot 4/Slice 1: 200 Mhz R4400 with 4 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 6.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 2 at Slot 4/Slice 2: 200 Mhz R4400 with 4 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 6.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 3 at Slot 4/Slice 3: 200 Mhz R4400 with 4 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 6.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 CPU Board at Slot 5: (Enabled) Processor 4 at Slot 5/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 5 at Slot 5/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 6 at Slot 5/Slice 2: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 7 at Slot 5/Slice 3: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 CPU Board at Slot 6: (Enabled) Processor 8 at Slot 6/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 9 at Slot 6/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 10 at Slot 6/Slice 2: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 11 at Slot 6/Slice 3: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 CPU Board at Slot 8: (Enabled) Processor 12 at Slot 8/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 13 at Slot 8/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 14 at Slot 8/Slice 2: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 15 at Slot 8/Slice 3: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 CPU Board at Slot 10: (Enabled) Processor 16 at Slot 10/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 17 at Slot 10/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 18 at Slot 10/Slice 2: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 19 at Slot 10/Slice 3: 150 Mhz R4400 with 1 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 5.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Main memory size: 1024 Mbytes, 2-way interleaved MC3 Memory Board at Slot 1: 256 MB of memory (Enabled) Bank A contains 16 MB SIMMS (Enabled) Bank B contains 16 MB SIMMS (Enabled) Bank C contains 16 MB SIMMS (Enabled) Bank D contains 16 MB SIMMS (Enabled) MC3 Memory Board at Slot 2: 512 MB of memory (Enabled) Bank A contains 16 MB SIMMS (Enabled) Bank B contains 16 MB SIMMS (Enabled) Bank C contains 16 MB SIMMS (Enabled) Bank D contains 16 MB SIMMS (Enabled) Bank E contains 16 MB SIMMS (Enabled) Bank F contains 16 MB SIMMS (Enabled) Bank G contains 16 MB SIMMS (Enabled) Bank H contains 16 MB SIMMS (Enabled) MC3 Memory Board at Slot 3: 256 MB of memory (Enabled) Bank A contains 16 MB SIMMS (Enabled) Bank B contains 16 MB SIMMS (Enabled) Bank C contains 16 MB SIMMS (Enabled) Bank D contains 16 MB SIMMS (Enabled) Instruction cache size: 16 Kbytes Data cache size: 16 Kbytes Secondary unified instruction/data cache size: 4 Mbytes Secondary unified instruction/data cache size: 4 Mbytes Secondary unified instruction/data cache size: 4 Mbytes Secondary unified instruction/data cache size: 4 Mbytes Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Integral SCSI controller 0: Version WD33C95A, differential, revision 0 Integral SCSI controller 1: Version WD33C95A, differential, revision 0 Disk drive: unit 1 on SCSI controller 1 (unit 1) Integral SCSI controller 2: Version SCIP/WD33C95A, single ended Integral SCSI controller 3: Version SCIP/WD33C95A, differential Integral SCSI controller 4: Version SCIP/WD33C95A, differential Integral SCSI controller 5: Version SCIP/WD33C95A, differential Integral SCSI controller 6: Version SCIP/WD33C95A, differential Disk drive: unit 1 on SCSI controller 6 (unit 1) Disk drive: unit 2 on SCSI controller 6 (unit 2) Integral SCSI controller 7: Version SCIP/WD33C95A, differential Disk drive: unit 1 on SCSI controller 7 (unit 1) Disk drive: unit 2 on SCSI controller 7 (unit 2) Disk drive: unit 3 on SCSI controller 7 (unit 3) # gfxinfo -v Graphics board 0 is "REV" graphics. Managed (":0.0") 1280x1024 Display 1280x1024 @ 72Hz 12 GE (GE10 rev. 0x7) 2 RM5 boards Medium pixel depth 10-bit RGBA pixels Not using Multi-Channel Option # hinv -c CPU Board at Slot 2: (Enabled) Processor 0 at Slot 2/Slice 0: 90 Mhz R8000 with 4 MB secondary cache (Enabled) Processor 1 at Slot 2/Slice 1: 90 Mhz R8000 with 4 MB secondary cache (Enabled) CPU: MIPS R8000 Processor Chip Revision: 3.0 FPU: MIPS R8010 Floating Point Chip Revision: 0.2 Main memory size: 512 Mbytes, 2-way interleaved MC3 Memory Board at Slot 1: 512 MB of memory (Enabled) Bank A contains 16 MB SIMMS (Enabled) Bank B contains 16 MB SIMMS (Enabled) Bank C contains 16 MB SIMMS (Enabled) Bank D contains 16 MB SIMMS (Enabled) Bank E contains 16 MB SIMMS (Enabled) Bank F contains 16 MB SIMMS (Enabled) Bank G contains 16 MB SIMMS (Enabled) Bank H contains 16 MB SIMMS (Enabled) Instruction cache size: 16 Kbytes Data cache size: 16 Kbytes Secondary unified instruction/data cache size: 4 Mbytes Integral SCSI controller 0: Version WD33C95A, single ended, revision 0 Disk drive: unit 1 on SCSI controller 0 (unit 1) Integral SCSI controller 1: Version WD33C95A, differential, revision 0 Disk drive: unit 1 on SCSI controller 1 (unit 1) Disk drive: unit 3 on SCSI controller 1 (unit 3) # gfxinfo -v Graphics board 0 is "RET" graphics. Managed (":0.0") 1280x2048 MCO Display 0 1280x1024 @ 60Hz, origin (0, 0) MCO Display 1 1280x1024 @ 60Hz, origin (0, 1024) 12 GE (GE10 rev. 0x7) 2 RM5 boards Small pixel depth 10-bit RGB pixels Driving Multi-Channel Option # hinv -c CPU Board at Slot 2: (Enabled) Processor 0 at Slot 2/Slice 0: 250 Mhz R4400 with 4 MB secondary cache (Enabled) Processor 1 at Slot 2/Slice 1: 250 Mhz R4400 with 4 MB secondary cache (Enabled) Processor 2 at Slot 2/Slice 2: 250 Mhz R4400 with 4 MB secondary cache (Enabled) Processor 3 at Slot 2/Slice 3: 250 Mhz R4400 with 4 MB secondary cache (Enabled) CPU: MIPS R4400 Processor Chip Revision: 6.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Main memory size: 1024 Mbytes, 2-way interleaved MC3 Memory Board at Slot 1: 1024 MB of memory (Enabled) Bank A contains 64 MB SIMMS (Enabled) Bank B contains 64 MB SIMMS (Enabled) Bank C contains 64 MB SIMMS (Enabled) Bank D contains 64 MB SIMMS (Enabled) Instruction cache size: 16 Kbytes Data cache size: 16 Kbytes Secondary unified instruction/data cache size: 4 Mbytes Integral SCSI controller 0: Version WD33C95A, single ended, revision 0 CDROM: unit 6 on SCSI controller 0 Integral SCSI controller 1: Version WD33C95A, differential, revision 0 Disk drive: unit 1 on SCSI controller 1 (unit 1) Disk drive: unit 2 on SCSI controller 1 (unit 2) Disk drive: unit 3 on SCSI controller 1 (unit 3) Disk drive: unit 4 on SCSI controller 1 (unit 4) Integral SCSI controller 5: Version SCIP/WD33C95A, differential Integral SCSI controller 6: Version SCIP/WD33C95A, differential Integral SCSI controller 7: Version SCIP/WD33C95A, differential # irix-gfxinfo Graphics board 0 is "KONA" graphics. Managed (":0.0") 1280x1024 Display has 2 channels 4 GEs (of 4), occmask = 0x0f 4MB external BEF ram, 32bit path 1 RM6 board (of 1) 1/0/0/0 Texture Memory: 16MB/-/-/- Medium pixel depth 32K cmap Channel 0: Origin = (0,0) Video Output: 1280 pixels, 1024 lines, 72.00Hz (1280x1024_72.vfo) # hinv -c CPU: MIPS R4400 Processor Chip Revision: 6.0 FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 CPU Board at Slot 2: (Enabled) Processor 0 at Slot 2/Slice 0: 250 Mhz R4400 with 4 MB secondary cache (Enabled) Processor 1 at Slot 2/Slice 1: 250 Mhz R4400 with 4 MB secondary cache (Enabled) Processor 2 at Slot 2/Slice 2: 250 Mhz R4400 with 4 MB secondary cache (Enabled) Processor 3 at Slot 2/Slice 3: 250 Mhz R4400 with 4 MB secondary cache (Enabled) CPU Board at Slot 3: (Enabled) Processor 4 at Slot 3/Slice 0: 150 Mhz R4400 with 1 MB secondary cache (Enabled) Processor 5 at Slot 3/Slice 1: 150 Mhz R4400 with 1 MB secondary cache (Enabled) Main memory size: 256 Mbytes, 2-way interleaved MC3 Memory Board at Slot 1: 256 MB of memory (Enabled) Bank A contains 16 MB SIMMS (Enabled) Bank B contains 16 MB SIMMS (Enabled) Bank C contains 16 MB SIMMS (Enabled) Bank D contains 16 MB SIMMS (Enabled) Instruction cache size: 16 Kbytes Data cache size: 16 Kbytes Secondary unified instruction/data cache size: 4 Mbytes Secondary unified instruction/data cache size: 4 Mbytes Secondary unified instruction/data cache size: 4 Mbytes Secondary unified instruction/data cache size: 4 Mbytes Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Integral SCSI controller 0: Version WD33C95A, single ended, revision 0 CDROM: unit 5 on SCSI controller 0 CDROM: unit 6 on SCSI controller 0 Integral SCSI controller 1: Version WD33C95A, differential, revision 0 Disk drive: unit 1 on SCSI controller 1 (unit 1) Disk drive: unit 2 on SCSI controller 1 (unit 2) Integral SCSI controller 40: Version WD33C95A, single ended, revision 0 Integral SCSI controller 41: Version WD33C95A, differential, revision 0